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Senior Design Verification Engineer

CYNET SYSTEMS - 189 Jobs
Markham, ON
Posted today
Job Details:
Full-time
Executive

Job Description:
Responsibilities:
  • Maintaining and enhancing verification environment and regression workflow.
  • Triaging and debugging regression results.
  • Analyzing test plan coverage.
  • Writing, modifying, and maintaining test cases and libraries in SystemVerilog/UVM/Ruby.
Personal Qualities And Key Skills:
  • Successful candidate should possess the following personal qualities and technical skills (5+ years):
  • Experience with SystemVerilog, Verilog and C/C++ is a must.
  • Strong understanding of the UVM-based verification methodology.
  • Experience with Low Power Verification and debug methodology is a must.
  • VCS/DVE familiarity is necessary.
  • Ability to juggle multiple on-going tasks at a time.
  • Strong, independent working ability.
  • Strong teamwork and communication skills.
  • Good attention to detail and creative thinking ability.

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