As a key contributor, you will define requirements, implement, and verify FPGA designs using VHDL and other modeling languages. This role involves participating in all stages of the design lifecycle, adhering to DO-254 or equivalent standards.

Responsibilities:

Translate product specifications into device-level requirements, including functional architecture, and derive and justify requirements.

Implement requirements in VHDL code, utilizing existing IPs and standard protocols (e.g., Omnibus, Ethernet, SPI, I2C, AMBA).

Conduct simulations, physical integration, and testing, including troubleshooting, debugging, and design adjustments.

Integrate the FPGA design into larger products or systems.

Create and maintain life-cycle data to support design, implementation, and verification.

Collaborate with project management to establish development logic, workflow, KPIs, and metrics for on-time, high-quality development and verification.

Qualifications:

Bachelor's Degree in Electrical or Computer Engineering (or equivalent), focusing on Digital Design.

5 years of FPGA/PLD development experience, preferably in aerospace, defense, or medical industries, using VHDL or similar languages.

Experience in architecture design, including trade-offs, partitioning, and allocation of complex device requirements.

Familiarity with DO-254 or similar guidelines to ensure rigorous and safe design processes.

Proficiency in designing and implementing interfaces between digital devices and microcontrollers, including data buses, communication protocols, and error handling.

Additional Considerations:

Experience with embedded control systems, ideally within aerospace and defense, including knowledge of system interfaces and sensors (e.g., RVDT/LVDT, BLDC motors, Servo Motors, temperature and pressure sensors, ARINC communications).

Ability to model and simulate systems using tools like MATLAB/Simulink is a plus.

Proficiency with the ModelSim toolset for VHDL design and verification.

Strong verbal and written communication skills.