UVM Verification Engineer - SystemVerilog / Verilog / OVM

• Are you a senior Verification Engineer with 10+ years' industry experience?
• Want to join a world semiconductor company focused on ASIC and FPGA design and verification, and embedded software in Canada?

We are partnered with an Ottawa HQ'd ASIC design house offering augmented design services and turnkey design teams within the semicon space. They are looking for a number of UVM Verification Engineers to join the team in Canada on a permanent basis.

They can offer hybrid work with some days spent onsite in Ottawa and can even support relocation to Canada so international applicants are encouraged.

Please note - remote work from outside Canada is not available

Sound good?

What will you do?

• Prime the verification activities for a block or an entire chip.
• Develop verification environment architecture using UVM
• Document test environment associations and write test cases
• Employ constrained random verification approaches when possible
• Support lab bring-up with direct test cases
• Perform code and functional coverage

What we look for in return is:

• 10+ years of experience in ASIC verification.
• Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
• Significant experience with OVM/UVM methodologies.
• Familiarity with constrained random verification techniques, assertions and functional coverage.

Any of the following will be considered a plus:

• Experience with SONET, OTN, Ethernet, PCIe is a significant asset.

If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your CV on

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